Low power consumption, high data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to reduce power consumption for semiconductor devices. As part of that effort to reduce power consumption, it may be desirable to include an input receiver circuit having a receiver of a low power “latch and amplify” type arranged as “an un-matched receiver” that may receive a signal with a small swing in an input buffer for receiving a signal. Such receiver is discussed in, for example, US 2015/0003574 A1 and may include a differential amplifier receiver and a sampler circuit. The differential amplifier receiver may receive a pair of complementary dock signals or a pair of complementary data strobe (DQS) signals and provide a clock/DQS signal with a delay equivalent to an internal delay to the sampler circuit. The sampler circuit may be a latch that may receive an address/command or data signal with a reference voltage
Unstable power source voltages and temperature cause delays in a differential amplifier receiver and a clock/DQS tree fluctuated and data reception error may occur. This can be explained by a deviation of a phase-level relationship between the received data and the Strobe/Clock in the sampler circuit (e.g., latch) caused in power-up operations or while receiving data. In order to confirm die fluctuations in the delays, a conventional example (JEDEC specification JESD209-4A Low Power Double Data Rate 4) shows a receiver circuit that includes a DQS interval oscillator. A memory controller may operate the oscillator for a predetermined period of time, and a memory unit executes measurements by using a counter and provides a count of the counter to the memory controller. Thus, the delay fluctuations in the differential amplifier and the strobe/CLK distribution tree may be observed. The memory controller may continuously obtain the fluctuations of the delays by comparing the delays between two counts of two timings, and determines whether a re-training (re-adjustment) process is executed. Because the fluctuations may be provided as counts in the oscillator in integer, a delay that corresponds to a value between two integers may be suppressed. Thus, a short measurement period may result in error of the delay measurement and a measurement period of about 50-100 ns may be required for the delay measurement. Thus, it is difficult to apply the oscillator for a measurement of a power-source fluctuation or the like of a short cycle (20 MHz or more). Moreover, fluctuations in a power supply voltage due to parallel resonance between a power-supply based inductance of a package and an on-die capacitance of a memory chip occurs near 20-100 MHz, and jitters of the receiver are increased as unrecoverable delay fluctuations to cause a high frequency operation dysfunctional. Furthermore, the memory controller is not able to interrupt ongoing memory access operations (e.g., read or write operation) and adjustment to the fluctuations by using intervals while in the ongoing memory access operations is difficult and inefficient, regardless necessity of adjustment observed by using the oscillator.